The present application relates to semiconductor structures, and more particularly to field effect transistor (FET) structures having asymmetric source and drain regions, and methods of manufacturing the same.
Standard FETs, as fabricated and used presently in the art, are symmetric devices in which source and drain regions are interchangeable. The source region and drain region in standard FETs have a same junction profile and are of a same conductivity type, either both n-type for n-type FETs (nFETs), or both p-type for p-type FETs (pFETs). Performance and radio frequency (RF) of classical FETs can be greatly enhanced by forming FETs with asymmetric source regions and drain regions. For example, tunnel FETs (TFETs) in which the source region and drain region are of different conductivity type are good candidates for low power integrated circuit applications due to their steep subthreshold slopes, normally below 60 mV/decade. In other instances, by providing an asymmetric design in source/drain junctions, the device performance of metal oxide semiconductor field effect transistors (MOSFETs) can also be significantly enhanced. In such an asymmetric design, more junction overlap on the source side may be created to reduce on-resistance (Ron). Simultaneously, the dopant profile at the drain side may be adjusted to obtain a reduced overlap, thereby reducing parasitic capacitance.
Fabrication of FETs with asymmetric source regions and drain regions is challenging because additional masks are needed in order to form source regions and drain regions separately, thus adding process complexity. As such, new fabrication methods are needed to reduce the process complexity in manufacturing the FETs with asymmetric source regions and drain regions.